There are several different types of memory devices and/or systems used in caches for computing environments, each having its own advantages and disadvantages. A static random access memory (SRAM) is commonly used in applications where access speed is a consideration. A conventional SRAM includes an array of bitcells. One traditional bitcell, i.e., a 6T bitcell, has two p-channel metal oxide semiconductor (PMOS transistor) transistors and four n-channel metal oxide semiconductor (NMOS) transistors.
In an SRAM bitcell, when writing data there is at least one NMOS transistor and at least one PMOS transistor that is subject to aging. One aging mechanism is called bias temperature instability. Bias temperature instability can be negative or positive, depending on the type of complementary metal-oxide-semiconductor (CMOS) transistor.
For example, a PMOS transistor commonly experiences negative bias temperature instability (NBTI) whereas an NMOS transistor commonly experiences positive bias temperature instability (PBTI). Negative bias temperature instability (NBTI) occurs when a PMOS transistor device continually experiences a negative bias across its gate oxide, with a low drain to source voltage. Positive bias temperature instability (PBTI) occurs when an NMOS device continually experiences a positive bias across its gate oxide with a low drain to source voltage. Aging due to both positive and negative bias temperature instability is currently the dominant aging mechanism in SRAM.
In an SRAM, VDD is the upper rail supply voltage or operating voltage, whereas VDDMIN can be characterized as the lowest voltage at which an SRAM bitcell can be reliably read from or written to for a given time. That is, VDDMIN is the voltage just above the voltage at which the first SRAM bitcell begins to fail. Foundries that create SRAM bitcells provide a conservative flat guard band for VDDMIN as commonly VDDMIN may increase due to aging in the SRAM transistors. Because the flat guard band is conservative, since it has to take into account the worst possible scenarios—i.e. the worst case stress conditions, worst case temperature, effects of aging, etc., what is needed is a technique to measure aging of an SRAM.